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copyright ? 201 5 future technology devices international limited 1 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 future technology devices international ltd . ft 600 /ft601 ( usb 3.0 to fifo bridge ) the ft 600 /ft601 is a usb 3.0 to fifo interface bridge chip with the following advanced features: ? support s usb 3.0 super speed (5gbps)/usb 2.0 high speed (480mbps)/usb 2.0 full speed (12mbps) transfer. ? supported usb transfer type: control/bulk/interrupt ? up to 8 configurable endpoints (pipes). ? support s 2 parallel slave fifo bus protocols 245 and fifo mode , ft601 with 32 bit parallel interface has a data bursting rate up to 400mb/s. ? support s 4 in channels and 4 out channels on fifo bus connectivity. ? built - in 16 k b fifo data b uffer ram. ? support s remote wakeup capability. ? support s multi v oltage i/o: 1.8v, 2.5v and 3.3v . ? configurable gpio support. ? internal ldo 1.0v regulator. ? integrated power - on - reset circuit. ? user programmable usb descriptors. ? supports battery chargin g spec . bc1.2. ? available as FT600 - 16bit/ft601 - 32bit fifo interface. ? industrial operating temperature range: - 40 to 85 ? ? available in compact pb - free qfn - 76( 32 bit ) and qfn - 56 ( 16bit ) packages (both rohs compliant). neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentat ion are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will not accept any claim for damages howsoever arising as a result of use or failure of this produ ct. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. this document provides preliminar y information that may be subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publication of this document. future technology devices international ltd, unit 1, 2 seaward place, centurion busine ss park, glasgow g41 1hh united kingdom . scotland registered company number: sc136640
copyright ? 201 5 future technology devices international limited 2 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 1 typical applications ? upgrading legacy peripherals to usb ? utilising usb to add system modularity ? interfacing pld/fpga based designs to usb 3 .0 ? usb 3.0 data acquisition ? usb 3.0 digital video camera interface ? usb 3.0 digital camera ? usb 3.0 interface for printer/ scanner ? medical /industrial imaging devices ? usb 3.0 instrumentation 1.1 driver support royalty free d3xx direct drivers (usb drivers + dll s/w interface) ? windows 8 ? windows 7 ? mac os - x (available late 2015) ? linux (available late 2015) the drivers listed above are all available to download for free from the ftdi website ( www.ftdichip.com ) . for driver installation, please refer to http://www.ftdichip.com/drivers/d3xx.htm 1.2 part numbers part number package ft 600 q - x 56 pin qfn 0.4mm pitch ft 601 q - x 76 pin qfn 0.4mm pitch table 1 . 1 device part numbers note: packaging codes for x is: - r: taped and reel, (vq fn in 3000 pieces per reel) - t: tray packing, (vqfn in 260 pieces per tray) for example: FT600q - r is 3000 qfn pieces in taped and reel packaging 1.3 usb compliant both FT600 and f t 601 are fully compliant with the usb 3.0 specification. usb if tid 340930018 applies to the FT600 and tid 340930019 for the ft601.
copyright ? 201 5 future technology devices international limited 3 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 2 block diagram figure 2 . 1 block diagram notes: FT600 q (qfn - 56) has a 16 - bit fifo bus interface and ft601 q (qfn - 76) has a 32 - bit fifo bus interface . for a description of each function please refer to section 4.
copyright ? 201 5 future technology devices international limited 4 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 table of contents 1 typical applications ................................ ................................ ...... 2 1.1 driver support ................................ ................................ .................... 2 1.2 part numbers ................................ ................................ ...................... 2 1.3 usb compliant ................................ ................................ .................... 2 2 block diagram ................................ ................................ .............. 3 3 device pin out and signal description ................................ .......... 5 3.1 device pin out ................................ ................................ .................... 5 3.2 device pin out signal descri ption ................................ ....................... 6 4 function description ................................ ................................ ..... 9 4.1 key features and function description ................................ ............... 9 4.2 multi - channel fifo mode protocols ................................ .................. 11 4.3 245 synchronous fifo mode protocols ................................ ............ 13 4.4 fifo bus ac timing ................................ ................................ ........... 15 5 devices characteristics and ratings ................................ ........... 16 5.1 absolute maximum ratings ................................ ............................... 16 5.2 esd and latch - up specifications ................................ ....................... 16 5.3 dc characteristics ................................ ................................ ............. 17 5.3.1 dc characteristics (ambient temperature = - 40c to +85c) ................. 17 5.3.2 dc characteristics for i/o interface ................................ ...................... 18 6 usb power configurations ................................ .......................... 19 6.1 usb bus - powered configuration ................................ ...................... 19 6.2 self - powered configuration ................................ .............................. 20 7 application example ................................ ................................ ... 21 7.1 FT600/ft601 connect to fifo master interface ............................... 21 8 package parameters ................................ ................................ ... 22 8.1 qfn - 56 package mechanical dimensions ................................ .......... 22 8.2 qfn - 56 package markings ................................ ................................ 23 8.3 qfn - 76 package mecha nical dimensions ................................ .......... 24 8.4 qfn - 76 package markings ................................ ................................ 25 appendix a C list of figures and tables ................................ .................... 27 appendix b C references ................................ ................................ ........... 28 appendix c C revision history ................................ ................................ ... 29
copyright ? 201 5 future technology devices international limited 5 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 3 device pin out and signal description 3.1 device pin out figure 3 . 1 qfn56 package pin out figure 3 . 2 qfn76 package pin out
copyright ? 201 5 future technology devices international limited 6 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 3.2 device pin out signal description pin nam 1 e description type pin no. qfn76 qf n56 clk parallel fifo bus clock output pin to fifo bus master , the frequency can be configure d as 66mhz or 100mhz for both fifo bus modes. o 58 43 data_0 parallel fifo bus data i/o bit 0. i/o 40 33 data_1 parallel fifo bus data i/o bit 1. i/o 41 34 data_2 parallel fifo bus data i/o bit 2. i/o 42 35 data_3 parallel fifo bus data i/o bit 3. i/o 43 36 data_4 parallel fifo bus data i/o bit 4. i/o 44 39 data_5 parallel fifo bus data i/o bit 5. i/o 45 40 data_6 parallel fifo bus data i/o bit 6. i/o 46 41 data_7 parallel fifo bus data i/o bit 7. i/o 47 42 data_8 parallel fifo bus data i/o bit 8. i/o 50 45 data_9 parallel fifo bus data i/o bit 9. i/o 51 46 data_10 parallel fifo bus data i/o bit 10. i/o 52 47 data_11 parallel fifo bus data i/o bit 11 . i/o 53 48 data_12 parallel fifo bus data i/o bit 12. i/o 54 53 data_13 parallel fifo bus data i/o bit 13. i/o 55 54 data_14 parallel fifo bus data i/o bit 14. i/o 56 55 data_15 parallel fifo bus data i/o bit 15. i/o 57 56 data_16 parallel fifo bus d ata i/o bit 16. i/o 60 n/a data_17 parallel fifo bus data i/o bit 17. i/o 61 n/a data_18 parallel fifo bus data i/o bit 18. i/o 62 n/a data_19 parallel fifo bus data i/o bit 19. i/o 63 n/a data_20 parallel fifo bus data i/o bit 20. i/o 64 n/a data_21 parallel fifo bus data i/o bit 21. i/o 65 n/a data_22 parallel fifo bus data i/o bit 22. i/o 66 n/a data_23 parallel fifo bus data i/o bit 23. i/o 67 n/a data_24 parallel fifo bus data i/o bit 24. i/o 69 n/a
copyright ? 201 5 future technology devices international limited 7 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 data_25 parallel fifo bus data i/o bit 25. i /o 70 n/a data_26 parallel fifo bus data i/o bit 26. i/o 71 n/a data_27 parallel fifo bus data i/o bit 27. i/o 72 n/a data_28 parallel fifo bus data i/o bit 28. i/o 73 n/a data_29 parallel fifo bus data i/o bit 29. i/o 74 n/a data_30 parallel fifo bus data i/o bit 30. i/o 75 n/a data_31 parallel fifo bus data i/o bit 31. i/o 76 n/a be_0 parallel fifo bus byte enable i/o bit 0. i/o 4 2 be_1 parallel fifo bus byte enable i/o bit 1. i/o 5 3 be_2 parallel fifo bus byte enable i/o bit 2. i/o 6 n/a be_3 parallel fifo bus byte enable i/o bit 3. i/o 7 n/a txe_n 245 synchronous fifo mode: transmit fifo empty output signal. the signal indicates there is a minimum of 1 byte of space available to write to. only write to the fifo when the signal is logic 0. m ulti - channel fifo mode: status valid output signal (optional). o 8 4 rxf_n 245 synchronous fifo mode : receive fifo full output signal. the signal indicates there is a minimum of 1 byte of data available to read. only read from the fifo when the signal is logic 0. multi - channel fifo mode : data receive acknowledge output signal. o 9 5 siwu_n reserve d. add external pull in normal operation. i 10 6 wr_n 245 synchronous fifo mode : write enable input signal. multi - channel fifo mode : data transaction request input signal. the signal is active low. i 11 7 rd_n 245 synchronous fifo mode : read enable inp ut signal. the signal is active low. i 12 8 oe_n 245 synchronous fifo mode : data output enable input signal. the signal is active low. o 13 9 reset_n chip reset input, active low . i 15 10
copyright ? 201 5 future technology devices international limited 8 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 wakeup _n suspend/remote wakeup pin. active low. i 16 11 reserv ed do not connect. i/o 19 14 gpio0 configurable gpio port0. i/o 17 12 gpio1 configurable gpio port1. i/o 18 13 vbus usb bus power input . i 37 29 xi crystal input . this terminal is the crystal input for the internal oscillator. i 21 16 xo crystal out put . this terminal is the crystal output for the internal oscillator. o 22 17 dp high - speed usb differential transceiver (positive) i/o 23 18 dm high - speed usb differential transceiver (negative) i/o 25 20 rref phy reference resistor input pin. connect 1.6k ? table 3 . 1 device pin out signal descriptions
copyright ? 201 5 future technology devices international limited 9 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 4 function description ft60 x is a high performance usb 3.0 - to - fifo interface bridge chip . this device can be used in those applications which require high data throughput such as imaging device s and multi - channel fifo adc or dac devices etc. the fifo interface can support multi - voltage i/o (1.8v, 2.5v, 3.3v) and operating freq uenc ies of 66.67mhz or 100mhz. 100mhz only for 2.5v and 3.3v. th ere are 2 different proprietary synchronous bus protocols supported; one fifo bus protocol is called the multi - channel fifo bus protocol and the o ther is the 245 synchronous fifo bus prot ocol. the latter being an extension of the interface introduced in the ft232h/ft2232h devices. 4.1 key features and function description functional integration. the following features are integral to the ic design: fifo protocol management, usb 3.0 controll er, usb3.0 and usb2.0 phys, gpios, power management, clock generation, power - on - reset (por) and ldo regulator . usb 3.0 protocol controller . the usb 3.0 protocol controller manages the data stream from the device usb control en dpoint. it handles the usb p rotocol requests generated by the usb host controller and the commands for controlling the functional parameters of the f ifo in accordance with the usb 3.0 specification. fifo management. this unit is used to manage all pipe data or buffer s in the fifo m emory; the data is sent or received through the fifo protocol layer. through this block the fifo memory can be allocated to each pipe with any size of memory as long as the total memory allocated to all pipes does not exceed the maximum fifo memory size wh ich is 16 k b . additionally, the fifo signals have a configurable high drive strength capabili ty and can be set to 18?, 25?, 35? and 50?. multi - channel fifo bus protocol. the multi - channel fifo bus is a s lave bus and is designed to handle multi - channel fifo connectiv ity. the bus protocol supports a total of 8 channels (4 ins and 4 outs). clk is the clock output to the fifo bus master. 245 synchronous fifo bus protocol. the 245 synchronous fifo bus is a slave bus with o ne in and one out fifo channel supported by this bus protocol. clk is the clock output to the fifo bus master. fifo bus clock options. the device provides 2 fifo bus clock frequency options: 66.67mhz and 100mhz. fifo rx /tx buffer ( 16k bytes). data sent from the usb host controller to the fifo via the usb data out endpoint is stored in the fifo rx (receive) buffer and is removed from the buffer by reading the contents of the fifo using the rd# pin. ( rx relative to the usb interface). data written into the fifo using the wr pin is stored in the fifo tx (transmit) buffer. the usb host controller removes data from the fifo tx buffer by sending a usb request for data from the device data in endpoint. (tx relative to the usb interface).
copyright ? 201 5 future technology devices international limited 10 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 when the FT600 or ft601 is configured as the 245 synchronous fifo bus or 1 channel in the multi - channel fifo bus mode , the fifo buffer is configured as 4 kb * 2 (double buffered) each on the rx and tx channel s . when the FT600 or ft601 is configured as 2 channel s in the multi - channel fifo bus mode, the fifo buffer is configured as 2 kb * 2 (double buffered) each on rx and tx channel. when the FT600 or ft601 is configured as 4 channel s in the multi - channel fifo bus mode, the fifo buffer is configured as 1 kb * 2 (double buffered) each on rx and tx channel. intern al ldo regulator. the ldo regulator generates the + 1.0v power supply for driving the internal core of the device. not to be used for external devices. reset generator. the integrated reset generator cell provides a reliable power - on reset to the device internal c ircuitry at power up. the reset_n input pin allows an external device to reset the ft60 x . active low. remote wake up function. if usb is in suspend mode, and remote wake up has been enabled, driving the wakeup_n pin to low will cause the ft60 x device to request a resume from suspend on the usb bus. normally this can be used to w ake up the host pc from suspend. bcd(battery charge detection) function. supports battery charging spec revision1.2, it is optional for mapping the gpio pin to indicat e the detect results. refer to gpio for the pin configuration in bcd mode , gpio (general purpose input and output) pins gpoi[1:0] are multifunction al pin s . t he function s are configured by the chip configuration data. the default chip configuration sets the gpio pin s as fifo mode configuration input. at the power up, FT600 or ft601 sets the chip to 245 synchronous fifo mode or multi - channel fifo mode s depend ing on the gpio [1:0] input , details in the table below: gpio1 gpio0 chip mode 0 0 1 channel, 24 5 synchronous fifo mode 0 1 1 channel, multi - channel fifo mode 1 0 2 channel, multi - channel fifo mode 1 1 4 channel, multi - channel fifo mode to enable the gpio function, the chip configuration must be updated to set the gpio function. t o enable the bcd mode, th e chip configuration must be updated to set the bcd mode. when the FT600 or ft601 is configured to support bcd, the gpio pins are set to output, output changes according to bcd detection result. gpio1 gpio0 chip mode 0 0 no usb connection or bcd detection on going. 0 1 sdp(standard downstream port) detected 1 0 cdp (charg ing downstream port) detected 1 1 dcp (dedicated charg ing port ) detected
copyright ? 201 5 future technology devices international limited 1 1 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 4.2 multi - channel fifo mode protocols this is a slave bus and is designed to handle multi - channel connectivity. the bus protocol supports a total of 8 channels (4 ins and 4 outs). clk is the clock output from the bus slave to the bus master. wr_n is the bus master to bus slave data transaction request signal, and it is active low . rxf_n is the bus slave to bus master data receive acknowledge signal, and it is active low . txe_n (optional signal , master can ignore this signal ) is the bus slave to bus master fifo idle status valid signal, and it is low active. data [31:0] is used as the 32 - bit data bus during the data transfer phase. when the bus is in the idle state data[31:16], data[7:0] and be [3:0] are driven to logic1 b y the bus master, and data [15:8] is driven by the bus slave to provide the fifo status to the bu s master . t he upper n ibble (data [15:12]) provide s the 4 out channels fifo s tatus while the lower nibble (data [11:8]) provide s the 4 in channels fifo status. they are all active low . for example, at idle , data[12] is logic0 and data [8] is logic0, which indicates usb out c hannel 1 fifo data is available to send and usb in channel 1 fifo space is empty to receive data respectively. the external b us master will start a transfer cycle by asserting wr_n based on the channel fifo status . the first cycle after wr_n is asserted is the command phase, follow ed by the data phase when rxf_n is asserted. at the command phase, the bus master will send the channel number which it intends to transfer data with on data [ 7:0] and the read/write command on be[3:0] . be[3:0] = h0 and be [3:0] = h1 indicate s a master read or write respectively. there may also be a required turn - a - round for data[31:0] and be [3:0] after the command phase and at the end of data transaction. be[1:0] is valid for FT600 2 byte wide data interface. table 4.1 sh ow s multi - channel fifo mode command phase master read/write and channel address setting. command phase FT600 command be[ 1 :0] ft601 command be[ 3 :0] channel address data[7:0] master read 00 00 00 8h1=channel 1 8h2=channel 2 8h3=channel 3 8h4=channel 4 table 4 . 1 multi - channel fifo mode command phase the waveform below shows a master read transaction of 10 bytes with fifo data exhausted first at channel 1 . there are turn - a - round c ycles for data [7:0], data [31:16] an d be [3:0] after command phase and at the end of the data transaction. the be[3:0] shows that the lower 2 bytes in d2 are valid at the last word strobe in this transaction. figure 4 . 1 multi - channel fifo mode master read transaction 1 i d l e c o m m a n d p h a s e d a t a o u t p u t b u s t u r n a r o u n d
copyright ? 201 5 future technology devices international limited 12 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 the waveform below shows a master read transaction for 1 2 valid bytes at channel 1 , w here the bus master terminates the transaction. there are turn - a - round cycles for data[7:0], data[31:1 6] and be [3:0] after the command phase and at the end of the data transaction. * the data is valid wh en wr_n and rxf_n are both active. figure 4 . 2 multi - channel fifo mode master read transaction 2 ? in m ulti - channel fifo mode master read operation, the bus master sh all be able to read out the maximum possible data in the rx fifo in one read transaction , i.e. when the FT600 or ft601 is configured in the 1 channel multi - channel fifo mode, the bus mast er sh all be able to read out 4 kb in one bus transaction, and 2 kb or 1 kb in respect to the 2 channel or 4 channel mode. in write operation, if the bus master expects the data to be transferred over usb bus in the maximum possible packet length, it shou ld write the data to the fifo in a single bus transaction. e.g. in a usb 3.0 super - speed connection with a packet size is 1 kb, and a fifo size of 4 kb, if the bus master completes the 4 kb in one transaction then the data will be transferred o n the usb bus in 4 full sized packets. if the bus master completes 1 kb in one transaction, the data will be transferred o n the usb bus in 1 packet. if the bus master completes 1025 bytes in one transaction, the data will be transferred over usb in 1 full siz ed packet and one short packet with 1 byte. the waveform below shows a master write transaction for 1 4 bytes at channel 1 with the bus master terminat ing the transaction. there are turn - a - round cycles for data [15:8] after the command phase and at the en d of the data transaction. the be[3:0] shows that the lower 2 bytes in d3 are valid at the last word strobe in this transaction. figure 4 . 3 multi - channel fifo mode master write transaction 1 h f
copyright ? 201 5 future technology devices international limited 13 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 note: the re is no turnaround phase for be pins as these remain inputs when the fifo is being written to by the master. the waveform below shows a master write transaction w here the fifo at channel 1 uses all data space first , the rxf_n deasserts when the fifo data space is not available after d3 . there are turn - a - round cycles for data [15:8] after the command phase and at the end of the data transaction . the be[3:0] shows that the transaction is all in word aligned , all 4 bytes in d3 are valid at the last word stro be in this transaction. figure 4 . 4 multi - channel fifo mode master write transaction 2 the waveform below shows a master read of channel 1 followed by a master write to channel 1 . the channel number is selected in the command phase (data[7:0] = h01 for channel 1 in this case) , and data is transferred on the same data pins multiplexed to a different channel. figure 4 . 5 multi - channel fifo mode master r ead followed by write transaction 4.3 245 synchronous fifo mode protocols this slave bus use s o ne in and one out fifo channel while in this mode . clk is the clock output to the bus master, it can be configured as 66mhz or 100mhz. txe_n is an output signal , transmit fifo empty . i t is active low and when active it indicates the transmit fifo has space and it is ready to receive data from the fifo master . rxf_n is an output signal, receive fifo full . i t is active low and when active it ind icates the receive fifo has data and it is ready to be read by the fifo master . oe_n is an input signal, output enable . i t is active low and when it is driven low by the bus master , the slave will drive the data and byte enable buses . wr_n is an input signal, write enable . i t is active low and when it is driven low by the bus master , the master has write cycle access. rd_n is an input signal, read enable . i t is active low and when it is driven low by the bus master , the master h as read cycle access. be[3:0](be[1:0] for FT600) is byte enable signal . in bus master read operation, the ft60 x assert s the signal for the valid bytes in a word strobe. in bus master write operation, the bus maste r assets the signal for the valid bytes in a word strobe. normally, all 4 bytes should be valid in a bus transaction except in the last word strobe when the data transaction length not aligned at word boundary.
copyright ? 201 5 future technology devices international limited 14 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 there are 2 waveforms below to show 245 sy nchronous fifo bus master write and read cycles. figure 4 . 6 245 synchronous fifo mode bus master read cycle ? in 24 5 synchronous fifo mode master read operation, the bus master shall be able to read out the maximum possible data in the rx fifo in one read transaction, i.e. the bus master shall be able to read out 4 kb in one bus transaction . in write operation s , if the bus master expects the data to be transferred on the usb bus in a maximum possible packet length, it should write the data to the fifo in a single bus transaction. e.g. in a usb 3.0 super - speed connection, with a packet size of 1 kb, and a fifo size of 4 kb, if the bus master completes the 4 kb in one transaction then the data will be transferred over the usb bus in 4 full sized packets. if the bus master completes 1 kb in one transaction, the data will be transferred over the usb bus in 1 packe t. if the bus master completes 1025 bytes in one transaction, the data will be transferred over usb in 1 full sized packet and one short packet with 1 byte. figure 4 . 7 245 synchronous fifo mode bus master write cycle
copyright ? 201 5 future technology devices international limited 15 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 4.4 fifo bus ac timing the FT600/ft60 1 device fifo bus is a synchronous parallel bus . t he clk sig nal is generated by the device , with the typical fifo clock duty cycle of 50%. both multi - channel and 245 synchronous f ifo mode s worst case ac timing are shown in figure 4.7 and table 4. 2 . in this figure, i nput data include s a ll control signals and data lines driven by the fifo master . output data include s all control signals and data lines driven by t he fifo slave - f t600/ft601 . figure 4 . 8 fifo bus ac timing diagram time description minimum maximum unit t1 slave drive data set up time 3.0 - ns t2 slave dri ve data hold time 3.5 - ns t3 master drive data set up time 2.3 - ns t4 master drive date hold time 3.8 - ns table 4 . 2 fifo bus ac timing clk o utput d ata t1 i nput d ata t2 t3 t4
copyright ? 201 5 future technology devices international limited 16 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 5 devices characteristics and ratings 5.1 absolute maximum ratings the absolute maximum ratings for the ft60 x devices are as follows. these are in acco rdance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. parameter value unit storage temperature - 65c to 150c degrees c ambient operating temperature (power applied) - 40c to 85c degrees c vcc 33/vdda supply voltage - 0.3 to +4.6 v vccio supply voltage - 0.3 to +4.0 v vd10 core supply voltage - 0.5 to +1.4 v avdd pll supply voltage - 0.5 to +1.4 v ios dc input voltage - 0.5 to + vccio+0.5 v table 5 . 1 absolute maximum ratings 5.2 esd and latch - up specifications description reference minimum typical maximum units
human body mode (hbm) jedec eia/jesd22 - a114 - b, class 2 - 2kv - kv machine mode (mm) jedec eia/jesd22 - a115 - a, class b - 200v - v charged device mode (cdm) jedec eia/ jesd22 - c101 - d, class - iii - 500v - v latch - up jesd78, trigger class - ii - 200ma - ma table 5 . 2 esd and latch - up specifications
copyright ? 201 5 future technology devices international limited 17 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 5.3 dc ch aracteristics 5.3.1 dc characteristics (ambient temperature = - 40c to +85c) parameter description minimum typical maximum units conditions vcc 33 /vdda vcc operating supply voltage 3.0 3.3 3.6 v vccio_1 vccio operating supply voltage 3.0 3.3 3.6 v vccio=3.3v vccio_2 vccio operating supply voltage 2.3 2.5 2.7 v vccio=2.5v vccio_3 vccio operating supply voltage 1.65 1.8 1.95 v vccio=1.8v vd10/avdd core/pll operating supply voltage 0.9 1.0 1.1 v icc _ 1 vcc operating supply current - 70 - ma idle, superspeed icc_2 vcc operating supply current - 65 - ma idle, high speed icc_ 3 vcc operating supply current - 185 - ma active, superspeed , multi - channel fifo mode icc _ 3 vcc operating supply current - 4 - m a usb suspend iccio_1 vccio operating supply current - 4 .5 - ma no data transfer iccio_ 2 vccio operating supply current 9 .5 ma data transfer iccio_ 3 vccio operating supply current 70 a usb suspend table 5 . 3 dc characteristics
copyright ? 201 5 future technology devices international limited 18 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 5.3.2 dc characteristi cs for i/o interface parameter description min typ max units conditions vccio_3.3v vccio operating supply voltage 3.0 3.3 3.6 v normal operation vccio_2.5v 2.3 2.5 2.7 v normal operation vccio_1.8v 1.65 1.8 1.95 v normal operation vih vccio*0.7 - - v normal operation vil - - vccio*0.3 v normal operation iin/iout(3.3v) input/output leakage - 10 - 10 ua without pull - up/down rpu/rpd input pull - up /pull down resistance 30 50 75 k? vout=0~ vccio iout(vccio=3.3v) output drive strength 10 - - ma total current iout(vccio=2.5v) output drive strength 9.4 - - ma total current iout(vccio=1.8v) output drive strength 5.0 - - ma total current cp pin capacitance - - 2.0 pf table 5 . 4 dc characteristics for i/o i nterface (except usb phy pins)
copyright ? 201 5 future technology devices international limited 19 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 6 usb power configurations the following sections illustrate possible usb power configurations for the ft60 x . the illustrations have omitte d pin numbers for ease of understanding since the pins differ between the FT600q and ft 601q package options. all usb power configurations illustrated apply to both package options for the ft60 x device s . please refer to section 3 for the package option pin - out and signal descriptions. 6.1 u sb bus - powered configuration note: the reference design s here are for usb 3.0 standard b or m icro - b connectors. figure 6 . 1 bus - powered configuration - 3.3v i / o figure 6 . 2 bus - powered configuration - 2.5v/1.8v i / o figure 6 . 1 & 6.2 i llustrate the ft60 x in a typical usb bus powered design configuration. a usb bus powered device gets its power from the usb bus via an external ldo stepping the voltage down to +3.3v .
copyright ? 201 5 future technology devices international limited 20 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 a ferrite bead is connected in series with the usb power supply to reduce emi noise from the ft60 x and associated circuitry being radiated down the usb cable to the usb host. the value of the ferrite bead depends on the total current drawn by the application. 6.2 self - powered configuration figure 6 . 3 self - powered configuration figure 6 . 3 illustrates the ft60 x in a typical usb self - po wered configuration. a usb self - powered device gets its powe r from its own power supply, vcc33 and vccio , and does not draw current from the usb bus. the basic rules for usb self - powered devic es are as follows C i) a self - powered device should not force current down the usb bus when the usb host or hub controller is powered down. ii) a self - powered device can use as much current as it needs during normal operation and usb suspend as it has its own pow er supply. iii) a self - powered device can be used with any usb host, a bus powered usb hub or a self - powered usb hub.
copyright ? 201 5 future technology devices international limited 21 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 7 application example the following sections illustrate possible applications of the ft60 x . the illustrations have omitted pin numbers for e ase of understanding since the pins differ between the FT600q and ft601 q package options. 7.1 FT600 /ft601 c onnect to fifo master interface figure 7 . 1 FT600 /ft601 connect to fifo master interface (multi - channe l fifo mode) figure 7 . 2 FT600 /ft601 connect to fifo master interface ( 245 synchronous fifo mode) a typical example of using the FT600 /ft601 as a usb 3.0 to fifo ma s ter interface is illustrated in figure 7 . 1 . and figure 7.2
copyright ? 201 5 future technology devices international limited 22 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 8 package parameters the ft60 x is available in two different packages base d on the fifo bus interface . the FT600q is the qfn - 56 package 16 - bit fifo bus interface and the ft601q is the qfn - 76 package 32 - bit fifo interface . 8.1 qfn - 56 package mechanical dimensions figure 8 . 1 qfn - 56 package dimensions the FT600q is suppl ied in a rohs compliant 56 pin qfn package. the package is lead (pb) free and uses a green compound. the package is fully compliant with european union directive 2002/95/ec. this pa ckage is nominally 7.0 mm x 7.0 mm body and the pins are on a 0.4 mm pitch . the above mec hanical drawing shows the qfn - 56 package. all dimensions are in millimetres. the cen tre pad on the base of the FT600 q is internally connected to gnd, the pcb should connect to ground and not have signal tracking on the same layer as the chip in this area.
copyright ? 201 5 future technology devices international limited 23 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 8.2 qfn - 56 package markings figure 8 . 2 qfn - 56 package markings notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment sho uld be centre justified 3. laser marking should be used 4. all marking dimensions should be marked proportionally. marking font should be using standard font (roman simplex) ftdi xxxxxxxxxx FT600q line 1 C ftdi logo line 4 C date code, revision line 2 C wafer lot number 1 56 line 3 C ftdi part number yyww - a
copyright ? 201 5 future technology devices international limited 24 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 8.3 qfn - 76 package mechanical dimensions figure 8 . 3 qfn - 76 package dimensions the ft601 q is supplied in a rohs compliant leadless qfn - 76 package. the package is lead ( pb ) free, and uses a green compound. the package is fully compliant with european union directive 2002/95/ec . this package is nominally 9.0 mm x 9.0 mm body. the solder pads are on a 0.4 0mm pitch. the above me c hanical drawing shows the qfn - 76 package. the centre pad on the base of the ft60 1q is internally connected to gnd , the pcb sho uld connect to ground and not have signal tracking on the same layer as chip in this area.
copyright ? 201 5 future technology devices international limited 25 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 8.4 qfn - 76 package markings figure 8 . 4 qfn - 76 package markings notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used 4. all marking dimensions should be marked proportionally. marking font should be using greatek standard font (roman simplex) ftdi xxxxxxxxxx ft601q line 1 C ftdi logo line 4 C date c ode, revision line 2 C wafer lot number 1 76 line 3 C ftdi part number yyww - a
copyright ? 201 5 future technology devices international limited 26 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 contact information head office C glasgow, uk unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan 2f, no. 516, sec. 1, neihu road taipei 114 taiwan, r.o.c. tel: +886 (0) 2 8797 1330 fax: +886 (0) 2 8751 9737 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C tigard , oregon, usa 7130 sw fir loop tigard , or 97223 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai, china room 1103 , no. 666 west huai h ai road, changn ing district shanghai, 200052 china tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://ftdichip.com system and equipment manufacturers and designers are responsible to ensure that their systems, and any future technology devices international ltd (ftdi) devices incorporated in their systems, meet all applicable safety, regulato ry and system - level performance requirements. all application - related information in this document (including application descriptions, suggested ftdi devices and other materials) is provided for reference only. while ftdi has taken care to assure it is ac curate, this information is subject to customer confirmation, and ftdi disclaims all liability for system designs and for any applications assistance provided by ftdi. use of ftdi devices in life support and/or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use. this document is subject to change without notice. no freedom to use patents or other intellectual property r ights is implied by the publication of this document. neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written conse nt of the copyright holder. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 201 5 future technology devices international limited 27 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 appendix a C list of figures and tables list of figures figure 2.1 block diagram ................................ ................................ ................................ .............. 3 figure 3.1 qfn56 package pin out ................................ ................................ ................................ .. 5 figure 3.2 qfn76 pack age pin out ................................ ................................ ................................ .. 5 figure 4.1 multi - channel fifo mode master read transaction 1 ................................ ........................ 11 figure 4.2 multi - channel fifo mode master read transaction 2 ................................ ........................ 12 figure 4.3 multi - channel fifo mode master write transaction 1 ................................ ....................... 12 figure 4.4 multi - channel fifo mode master write transaction 2 ................................ ....................... 13 figure 4.5 multi - channel fifo mode master read followed by write transaction ................................ .. 13 figure 4.6 245 synchronous fifo mode bus master read cycle ................................ ........................ 14 figure 4.7 245 synchronous fifo mode bus master write cycle ................................ ........................ 14 figure 4.8 fifo bus ac timing diagram ................................ ................................ ......................... 15 figure 6.1 bus - powered configuration - 3.3v i/o ................................ ................................ .............. 19 figure 6.2 bus - powered configuration - 2.5v/1.8v i/o ................................ ................................ ...... 19 figure 6.3 self - powered configuration ................................ ................................ ........................... 20 figure 7.1 ft60 0/ft601 connect to fifo master interface (multi - channel fifo mode) ........................ 21 figure 7.2 FT600/ft601 connect to fifo master interface (24 5 synchronous fifo mode) .................. 21 figure 8.1 qfn - 56 package dimensions ................................ ................................ ........................ 22 figure 8.2 qfn - 56 package markings ................................ ................................ ........................... 23 figure 8.3 qfn - 7 6 package dimensions ................................ ................................ ........................ 24 figure 8.4 qfn - 76 package markings ................................ ................................ ........................... 25 list of tables table 1.1 device part numbers ................................ ................................ ................................ ....... 2 table 3.1 device pin out signal descriptions ................................ ................................ ..................... 8 table 4.1 multi - channel fifo mode command phase ................................ ................................ ...... 11 table 4.2 fifo bus ac timing ................................ ................................ ................................ ....... 15 table 5.1 absolute maximum ratings ................................ ................................ ............................ 16 table 5.2 esd and latch - up specifications ................................ ................................ .................... 16 table 5.3 dc characteristics ................................ ................................ ................................ ........ 17 table 5.4 dc characteristics for i/o interface (except usb phy pins) ................................ ................ 18
copyright ? 201 5 future technology devices international limited 28 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 appendix b C references useful application notes an_379 d3 xx programmers guide an_375 FT600 data loopback application user guide modules datasheet ds_umft60xx module datasheet data loopback application FT600dataloopback
copyright ? 201 5 future technology devices international limited 29 ds_FT600q - ft601q ic datasheet /ft601 usb 3.0 to fifo bridge version 1.01 document no.: ft_001118 clearance no.: ftdi#424 appendix c C revision history document title: usb 3.0 to fifo bridge document reference no.: ft_ 001118 clearance no.: ftdi# 424 product page: http://www.ftdichip.com/ftproducts.htm document feedback: send feedback revision changes date 1.0 initial release 2015/07/07 1.01 update d figure 4.7 & table 3.1 2015/0 9 / 0 8

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